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NXP Semiconductors /QN908XC /SYSCON /PIO_CFG_MISC

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Interpret as PIO_CFG_MISC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PB00_AE)PB00_AE 0 (PB01_AE)PB01_AE 0 (PSYNC)PSYNC 0 (BOOT_MODE)PB02_MODE 0 (TRX_EN_POL)TRX_EN_INV 0 (RFE_POL)RFE_INV

PB02_MODE=BOOT_MODE, RFE_INV=RFE_POL, TRX_EN_INV=TRX_EN_POL

Description

pin misc control register

Fields

PB00_AE

Enable PB00 analog function
PB01_AE

Enable PB01 analog function
PSYNC

when 1, bypass first stage of synchronization of DMA pin trigger
PB02_MODE

chip mode pin function select

0 (BOOT_MODE): PB02 is used as chip mode input

1 (ANTENNA): PB02 is used as antena output
TRX_EN_INV

inverse TX_EN & RX_EN pin mux output polarity

0 (TRX_EN_POL): inverse TX_EN & RX_EN pin mux output polarity
RFE_INV

Inverse RFE polarity

0 (RFE_POL): Inverse RFE polarity

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data